Published by: VhdlCohen Publishing P. Copyright by VhdlCohen Publishing All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without the prior written permission from the author, except for the inclusion of brief quotations in a review. Printed on acid-free paper Printed in the United States of America. Contents Foreword Janick Bergeron
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Published by: VhdlCohen Publishing P. Copyright by VhdlCohen Publishing All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without the prior written permission from the author, except for the inclusion of brief quotations in a review. Printed on acid-free paper Printed in the United States of America. Contents Foreword Janick Bergeron Stuart Sutherland Scott Sandler Alain Raynaud Acknowledgements About the Authors Disclaimer 1 1.
Why SystemVerilog for Verification SystemVerilog Constructs Supporting Verification.. Why VMM? Testbench architecture with VMM. Layered testbench architecture Testbench Outline. Creation of channels Access to Elements in a Channel Channel allocation Channel reconfiguration..
File Structure Atomic generator.. Simple atomic generator.. Scenario generator Command-Layer Transactor.. Factory Definition Factory Example constraints Custom Generator Architecture..
Notification of Completion Generator Design.. Simulation of Custom Generator VMM Scenario Generator Handling multiple scenarios Creating dummy sinks for Channel outputs.. Using a Nonblocking Channel.. Using an artificial sink transactor VMM Scheduler Functional Coverage Extracting coverage points Integrating coverage models into the environment Seeding the Randomization.. Changing error severity dynamically.. And it is getting worse. The verification aspect of SystemVerilog was designed to bring the power and productivity of Hardware Verification Languages to the industry at large, within the familiar framework of the Verilog language.
However, based on my many years of experience using and teaching HVLs, I knew that it would be a slow and difficult process for new adopters to realize all of its potential and benefits unless a clear path was provided. With three other experts in other area of functional verification, we set out to provide that path as the Verification Methodology Manual for SystemVerilog.
Then there is the question of the form the path should take. Should it be a path that takes users from simple, purely directed Verilog testbenches to constrained-random testbenches, exploring along the way how various SystemVerilog constructs are used most effectively? Or should it be a clear definition of the end goal, a set of minimum practices that must be used to create interoperable and reusable verification assets?
Should it be a training vehicle or a methodology? As the name of the VMM suggests, we chose the latter form. A methodology is about what should and should not be done to be as productive as possible. There must be a clear indication of whether or not a testbench or a transactor is compliant to the methodology. A methodology cannot be a training vehicle nor can a training vehicle claim to be a methodology. A methodology and the training it requires to learn it and apply it effectively are two different things.
We fully expected that training and introductory material would appear to help adopt the methodology described in the VMM just like there are several introductory books and training classes on the Verilog language and its usage, despite the fact that it is fully specified in an IEEE standard document.
VMM-related conference papers have also already started to appear. I am pleased to welcome this book to the cannon of VMM literature. I hope you will find it helpful in appreciating the power of the VMM methodology and ease your adoption of it.
It has several drawers, and each drawer has many tools neatly laid out side-by-side. I also have a repair manual on how to work on the 35 year old Volkswagen beetle that is parked in my garage; a project car that my son and I are working on. Unfortunatelyespecially for the carhaving the tools and manuals is not enough to make me a qualified auto mechanic.
The shop manual tells me what to do, but not which tool to use. Even if I happen to select the correct tool for the repair at hand, I find myself reading and rereading the same paragraph in the manual in a vain attempt to make the description and pictures in the manual match what I am looking at when lying underneath the car looking up at the greasy underside of the engine or transmission.
And having all those tools and a manual do not seem to help a bit when Im trying to figure out in what order to reassemble the 40 or more pieces that make up the front brake assembly and wheel bearings. SystemVerilog adds to the programming and verification constructs of Verilog many new data types, new programming statements, dynamic arrays, associative arrays, process synchronization, mailboxes, direct calls to C, and Object-Oriented programming an entire tool set, in an of itself. The constructs and capabilities of SystemVerilog, if they were mechanical tools arranged neatly in a tool chest, would be the envy of mechanics everywhere.
The VMM is not a simple manual that a novice engineer can just pick up and make sense of. It shouldn't be. The VMM presents a complex and robust methodology that can handle any size of design and any type of design, and at the same time, a methodology that can scale and be re-used for the verification of many future designs.
SystemVerilog gives us the tools, and the VMM gives us the methodology. Somewhere along the way, we need to figure out how to pick the right tool or tools from the SystemVerilog tool chest, and use those tools in the way the VMM recommends. This book teaches by example how the constructs in SystemVerilog are used to implement the methodology presented in the VMM. Similar to learning from an experienced mechanic how to use the right tools to repair a car, this book provides a way to learn from experts the right way to use SystemVerilog for verification.
With the help of these experts, it is much easier to understand how to apply the methodology presented in the VMM on actual designs. This book does not replace having a copy of the Verilog and SystemVerilog standards or good books about those standards. Nor does this book replace having a copy of the VMM. The language reference books, the VMM and this book should be used together. The book is an invaluable resource to all engineers who need to apply SystemVerilog in the verification of designs.
Next, I wonder if Ben and his co-authors can write a book to help make it obvious how to make the text and pictures in my auto repair manual map to the greasy underside of my VW beetle! Sutherland HDL provides expert level training on how to correctly use Verilog and SystemVerilog, with specialized courses on synthesis, verification, and assertions.
Developing semi-structured approaches has consumed countless years of project and people time, costing the semiconductor industry billions.
The growth of integrated circuit complexity has driven the effort required beyond all reason. The advent of Hardware Verification Languages brought the promise of more structure and the potential for great savings. SystemVerilog takes things a couple of steps further by combining design and verification in a single language while retaining the simple elegance of Verilog and adding the modern object-oriented programming capabilities that are key to saving time in complex software projects.
Like any powerful medium, the promise and potential of SystemVerilog comes with the risk of getting bogged down in even more complexity. The emergence of VMM has helped to organize and structure the efforts of design and verification teams adopting SystemVerilog to help them avoid that pitfall.
Now once again, Ben Cohen and his co-authors have done the industry a real service by making a powerful technique even more accessible. Our work at Novas is aimed at making the complex more easily understood. We believe that standards and standardized methodologies are organizing principles that allow the entire semiconductor industry to continue moving forward at its remarkable pace. Building support for the whole of SystemVerilog into our products has been a significant effort, and well worthwhile, as it allows our users to leverage VMM and this book to find and resolve more bugs faster!
As users start adopting SystemVerilog, they are especially curious of the new testbench constructs and frameworks offered by the language. The Verification Methodology Manual VMM is a SystemVerilog-based framework that arrived just in time to put some order in a situation that was about to become chaotic.
It remains to be seen if the VMM will become the standard for verification testbenches, just like RTL became the standard subset for synthesis, but this book will serve as a stepping stone for all users wanting to learn about the VMM by example. In the area of hardwareassisted acceleration and emulation especially, off-the-shelf FPGAs have won the battle for speed.
However, accelerating the verification of a design is of no value if its testbench cant keep up. But thanks to the work of the Interface Technical Committee ITC at Accellera, the technology is ready today to allow testbenches to exchange data with designs emulating at multiple MHz. What had limited the usefulness of those hardware transactors until today was the manual effort required to retrofit them into old, poorly structured testbenches. The VMM in that regard is the missing link to an efficient verification flow, from well-structured, reusable and easy to maintain testbench in simulation to accelerated simulation where both design and testbench run at speeds previously unheard of.
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Coding Forums. With SystemVerilog becoming an IEEE standard, there is a growing user momentum in adopting this powerful language as it unified design, assertions and testbench. This is where a methodology and a framework really helps - it shifts the focus from language constructs to the actual goal - of building verification environments and the verification process itself. The recently published VMM book has attracted lots of interest in the user community with over copies sold so far. VMM represents a methodology that includes a set of minimum practices that must be used to create interoperable and reusable verification assets.
New Book: A Pragmatic Approach to VMM Adoption // for TB designs
This book is intended to help you come up to speed in the design of SystemVerilog transaction-based testbenches that comply with the Verification Methodology Manual VMM. The goals of this book are to help you adopt, with complete, compilable, and executable examples, the VMM methodology in the creation of comprehensive constrained-random and directed verification environments using a transaction-level modeling TLM approach. All code examples are available for download. Convert currency.