You are currently using the site but have requested a page in the site. Would you like to change to the site? Miron Abramovici , Melvin A. Breuer , Arthur D. Considered a definitive text in this area, the book includes in-depth discussions of the following topics:. Test generation Fault modeling for classic and new technologies Simulation Fault simulation Design for testability Built-in self-test Diagnosis.

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For general information on our other products and services please contact our Customer Care Department within the U. ISBN Printed in the United States of America 10 9 8 To our families, who were not able to see their spouses and fathers for many evenings and weekends, and who grew tired of hearing "leave me alone, I'm working on the book. We love you. These subjects are increasingly important, as the cost of testing is becoming the major component of the manufacturing cost of a new product.

Today, design and test are no longer separate issues. The emphasis on the quality of the shipped products, coupled with the growing complexity of VLSI designs, require testing issues to be considered early in the design process so that the design can be modified to simplify the testing process. This book was designed for use as a text for graduate students, as a comprehensive reference for researchers, and as a source of information for engineers interested in test technology chip and system designers, test engineers, CAD developers, etc.

To satisfy the different needs of its intended readership the book 1 covers thoroughly both the fundamental concepts and the latest advances in this rapidly changing field, 2 presents only theoretical material that supports practical applications, 3 provides extensive discussion of testable design techniques, and 4 examines many circuit structures used to realize built-in self-test and self-checking features.

Chapter 1 introduces the main concepts and the basic terminology used in testing. Modeling techniques are the subject of Chapter 2, which discusses functional and structural models for digital circuits and systems. Chapter 3 presents the use of logic simulation as a tool for design verification testing, and describes compiled and event-driven simulation algorithms, delay models, and hardware accelerators for simulation.

Chapter 4 deals with representing physical faults by logical faults and explains the concepts of fault detection, redundancy, and the fault relations of equivalence and dominance. The most important fault model - the single stuck-fault model - is analyzed in detail. Chapter 5 examines fault simulation methods, starting with general techniques - serial, parallel, deductive, and concurrent - and continuing with techniques specialized for combinational circuits - parallel-pattern single-fault propagation and critical path tracing.

Finally, it considers approximate methods such as fault sampling and statistical fault analysis. Chapter 6 addresses the problem of test generation for single stuck faults. It first introduces general concepts common to most test generation algorithms, such as implication, sensitization, justification, decision tree, implicit enumeration, and backtracking.

Other topics include random test generation, test generation for sequential circuits, test generation using high-level models, and test generation systems. Chapter 7 looks at bridging faults caused by shorts between normally unconnected signal lines. Although bridging faults are a "nonclassical" fault model, they are dealt with by simple extensions of the techniques used for single stuck faults. Chapter 8 is concerned with functional testing and describes heuristic methods, techniques using binary decision diagrams, exhaustive and pseudoexhaustive testing, and testing methods for microprocessors.

Chapter lOis dedicated to compression techniques, which consider a compressed representation of the response of the circuit under test. The techniques examined are ones counting, transition counting, parity checking, syndrome checking, and signature analysis. Because of its widespread use, signature analysis is discussed in detail. The main application of compression techniques is in circuits featuring built-in self-test, where both the generation of input test patterns and the compression of the output response are done by circuitry embedded in the circuit under test.

Chapter 12 discusses logic-level diagnosis. The covered topics include the basic concepts in fault location, fault dictionaries, guided-probe testing, expert systems for diagnosis, effect-cause analysis, and a reasoning method using artificial intelligence concepts.

Chapter 13 presents self-checking circuits where faults are detected by a subcircuit called a checker. Self-checking circuits rely on the use of coded inputs. Some basic concepts of coding theory are first reviewed, followed by a discussion of specific codes - parity-check codes, Berger codes, and residue codes - and of designs of checkers for these codes.

Chapter 14 surveys the testing of programmable logic arrays PLAs. First it reviews the fault models specific to PLAs and test generation methods for external testing of these faults. Then it describes and compares many built-in self-test design methods for PLAs. Chapter 15 deals with the problem of testing and diagnosis of a system composed of several independent processing elements units , where one unit can test and diagnose other units.

The focus is on the relation between the structure of the system and the levels of diagnosability that can be achieved. In the Classroom This book is designed as a text for graduate students in computer engineering, electrical engineering, or computer science. The book is self-contained, most topics being covered extensively, from fundamental concepts to advanced techniques. We assume that the students have had basic courses in logic design, computer science, and probability theory.

Most algorithms are presented in the form of pseudocode in an easily understood format. The progression of topics follows a logical sequence where most chapters rely on material presented in preceding chapters.

The most important precedence relations among chapters are illustrated in the following diagram. For example, fault simulation 5 requires understanding of logic simulation 3 and fault modeling 4. Design for xv testability 9 and compression techniques 10 are prerequisites for built-in self-test Modeling 3.

Logic Simulation 4. Fault Modeling 5. Fault Simulation 6. Testing for Single Stuck Faults 8. Functional Testing 9. Design for Testability Compression Techniques Self-Checking Design PLA Testing Built-In Self-Test System-Level Diagnosis Precedence relations among chapters The book requires a two-semester sequence, and even then some material may have to be glossed over.

For a one-semester course, we suggest a "skinny path" through Chapters 1 through 6 and 9 through The instructor can hope to cover only about half of this material. This "Introduction to Testing" course should emphasize the fundamental concepts, algorithms, and design techniques, and make only occasional forays into the more advanced topics.

Among the subjects that could be skipped or only briefly discussed in the introductory course are Simulation Engines Section 3. Most of the material in Chapter 2 and the ad hoc design for testability techniques 9. Most of the topics not included in the introductory course can be covered in a second semester "Advanced Testing" course.

Acknowledgments We have received considerable help in developing this book. Special thanks go to the Bell Labs word processing staff - Yvonne Anderson, Deborah Angell, Genevieve Przeor, and Lillian Pilz - for their superb job in producing this book, to David Hong for helping with troff and related topics, to Jim Coplien for providing the indexing software, and to John Pautler and Tim Norris for helping with the phototypesetter.

We want to thank our many colleagues who have been using preprints of this book for several years and who have given us invaluable feedback, and especially S. Reddy, S. Seth, and G. And finally, many thanks to our students at the University of Southern California and the Illinois Institute of Technology, who helped in "debugging" the preliminary versions.

Miron Abramovici Melvin A. Breuer Arthur D. We will not begin by saying that "because of the rapid increases in the complexity of VLSI circuitry, the issues of testing, design-for-test and built-in-self-test, are becoming increasingly more important.

Instead, we will tell you a little of the background of this book. The story started at the end of He suggested co-authoring a new book, using as much material from the yellow book as possible and updating it where necessary. He would do most of the writing, which Mel and Art would edit. It all sounded simple enough, and work began in early Two years later, Miron had written less than one-third of the book. Most of the work turned out to be new writing rather than updating the yellow book.

The subjects of modeling, simulation, fault modeling, fault simulation, and test generation were reorganized and greatly expanded, each being treated in a separate chapter. The end, however, was nowhere in sight. Late one night Miron, in a state of panic and frustration, and Mel, in a state of weakness, devised a new course of action. Miron would finalize the above topics and add new chapters on bridging faults testing, functional testing, logic-level diagnosis, delay-faults testing, and RAM testing.

Mel would write the chapters dealing with new material, namely, PLA testing, MOS circuit testing, design for testability, compression techniques, and built-in self-test. And Art would update the material on self-checking circuits and system-level diagnosis. The years went by, and so did the deadlines.

Only Art completed his chapters on time. The book started to look like an encyclopedia, with the chapter on MOS testing growing into a book in itself. Trying to keep the material up to date was a continuous and endless struggle. Finally we acknowledged that our plan wasn't working and adopted a new course of action. Mel would set aside the MaS chapter and would concentrate on other, more essential chapters, leaving MaS for a future edition.

Miron's chapters on delay fault testing and RAM testing would have the same fate. A new final completion date was set for January This plan worked, though we missed our deadline by some 10 months. Out of love for our work and our profession, we have finally accomplished what we had set out to do.

As this preface was being written, Miron called Mel to tell him about a paper he just read with some nice results on test generation. Yes, the book is obsolete already.

If you are a young, energetic researcher - don't call us. If incorrect behavior is detected, a second goal of a testing experiment may be to diagnose, or locate, the cause of the misbehavior.


Digital systems testing and testable design

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Digital Systems Testing and Testable Design

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Digital Systems Testing and Testable Design - Miron Abramovici, Melvin a. Breuer, D Arthur Friedman




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